Hi3559AV100 Hisilicon
Key Features
Processor Core- Dual-core ARM Cortex [email protected], 32KB I-Cache, 64KB D-Cache /512KB L2 cache
- Dual-core ARM Cortex [email protected], 32KB I-Cache, 32KB D-Cache /256KB L2 cache - Single-core ARM Cortex [email protected], 32KB I-Cache, 32KB D-Cache /128KB L2 cache - Neon acceleration support, integrated FPU processing unit |
GPU- Dual-core ARM Mali G71@900MHz, 256KB cache
- Support OpenCL 1.1/1.2/2.0 - Support OpenGL ES 3.0/3.1/3.2 |
Sensor Hub- Integrated ARM Cortex M7@192Mhz
- Integrated PMC power control unit, PMC only supports external reset - Supports internal POR - Supports general-purpose peripheral IP (UART/SPI/I2C/PWM/GPIO/LSADC) - Support 2-channel LSADC, 7 UART interfaces, 8 PWM interfaces |
Video Encoding- H.264 BP/MP/HP |
Video Decoding- Support H.264 BP/MP/HP
- Support H.265 Main Profile/Main 10 Profile - Supports JPEG/MJPEG Baseline - Support up to H264/H.265 7680 x 4320@30fps or H.264/H.265 3840 x 2160@120fps. - Supports JPEG decoding up to 7680 x 4320@15fps. |
Intelligent Video Processing- Provides visual computing processing power
- Quad-core DSP@700MHz, 32K I-Cache /32K IRAM/512KB DRAM - Dual-core NNIE@840MHz neural network acceleration engine - Built-in binocular depth detection unit |
Video and Graphics Processing- Support video and graphic output anti-flicker processing
- Support video 1/15.5 ~ 16x zoom function - Support up to 6-way video 360°/720° panoramic splicing - Support 1/15.5~16x zoom function for graphics - 8 regions of pre-code processing OSD overlay - 2-layer (video layer, graphics layer) video graphics overlay |
ISP- Support two independent ISP processing, ISP support time division processing of multiple sensor input video |
Audio Codec- Realize multi-protocol voice codec through software
- Supports G.711/G.726/AAC/etc. audio coding formats. - Supports audio 3A (AEC/ANR/ALC) processing. |
Security Engine- Hardware implementation of AES/DES/3DES encryption and decryption algorithms
- Hardware implementation of RSA1024/2048/3072/4096 signature verification algorithm. - Hardware implementation of HASH anti-tampering algorithm, supports HASH SHA1/224/256/384/512 and HMAC_SHA1/224/256/384/512 algorithms. - Internal 32KBit OTP memory and hardware random number generator. |
Video Interface- Input |
Audio Interface- Integrated Audio codec, support 16bit voice input and output
- Supports I2S interface and external Audio codec. - Supports dual-channel Mic differential input to reduce noise floor |
Peripheral Interface- Support POR
- Supports external reset input - Supports internal RTC - Integrated 2-channel LSADC - 5 UART interfaces - IR interface, I2C interface, SSP main interface, GPIO interface - Integrated 2 GMACs, support RGMII/RMII interface - 2 PWM interfaces - 2 SD3.0/SDIO3.0 interfaces, 1 SD2.0 interface - 2x USB3.0/USB2.0 Host/Device interfaces - 2xlane PCIe2.0 RC/EP mode |
External Memory Interface- DDR4/LPDDR4 interface |
SDK- Support Linux SMP
- Support Linux + HUAWEI LiteOS dual system AMP - Provides high-performance H.265 decoder library |
Chip Physical Specifications- Power Consumption
-3W typical power consumption (4K120) -Supports multi-level power saving mode - Operating Voltage -Kernel voltage is 0.8V -IO voltage is 1.8V -DDR4 SDRAM interface voltage of 1.2V -LPDDR4 interface voltage of 1.1V - Package Format -RoHS, FC-BGA -25mm x 25mm package size -Pin pitch: 0.65mm |
